Fundamentals of VLSI Chip Design

Fundamentals of VLSI Chip Design

INSTRUCTOR: TUMMALA BHANU

VLSI Design:

• What is VLSI?

• “Very Large Scale Integration”
• Defines integration level
• 1980s hold-over from outdatedtaxonomy for integration levels

• Obviously influenced from
frequency bands, i.e. HF, VHF, UHF

• Sources disagree on what is measured (gates or transistors?)

• SSI – Small-Scale Integration (0-102)
• MSI – Medium-Scale Integration (102-103)
• LSI – Large-Scale Integration (103-105)
• VLSI – Very Large-Scale Integration (105-107)
• ULSI – Ultra Large-Scale Integration (>=107)

Integration Level Trends:

Obligatory historical Moore’s law plot

Integrated Circuits/MEMs:

• Today, VLSI refers to systems impl. w/integrated circuits

• Integrated circuit refers mostly togeneral manufacturing technique

• micro/nano-scale devices on a semiconductor (crystalline) substrate

• Formed using chemical/lithography processing

• What kind of devices / structures?

• transistors (bipolar, MOSFET)
• wires (interconnects and passive devices)
• diodes (junction, LEDs, VCSELs, MSM, photoconductor, PiN)

• MEMs (integration of piezoelectrics and mechanics based on static electrical fields: accelerometers, gyroscopes, pressure sensors, micro-mirrors)

• For CMOS digital design, we only use MOSFET transistors (used as switches) and wires

Chips:

• Integrated circuits consist of:
• A small square or rectangular “die”, < 1mm thick

• Small die: 1.5 mm x 1.5 mm => 2.25 mm2

• Large die: 15 mm x 15 mm =>

225 mm2

• Larger die sizes mean:

• More logic, memory

• Less volume

• Less yield

• Dies are made from silicon (substrate)

• Substrate provides mechanical support and electrical common point

VLSI Design:

• Draw polygons that represent layers deposited-on or infused-into the substrate

• More of an art than science

• One 2-input NAND gate with 4 transistors

• Typical microprocessor contains 50 – 200 million transistors (10-50 million gates)

VLSI Design:

• Manual layout design is obviously not practical
• Design complexity:

• Manually drawing layout for a billion transistors would take too long

• Even if we could…

• How to verify (test) designs for functionality, speed, power, etc.?

• Complexity scales faster than actual design

• How to reuse designs?

• How to create human-readable designs?

• How to speed-up design process?

• These problems form a great deal of work

• Electronic Design Automation (EDA)
• a.k.a. CAD

• Advancing EDA technology, fabrication technology, designs and micro architectures, and IP form bulk of work (and money) in the industry

Course Overview:

• This course is called “Fundamentals of VLSI Chip Design”
• Focus on large-scale system design (CAD tools)
• CAD tools manage design and verification complexity
• What we have…

• Latest, most advanced CAD tools in the EDA industry

• Three primary players

• Synopsys, #258 ($1.2 billion revenue)

• Cadence Design Systems, #259 ($1.1 billion revenue)

• Mentor Graphics, ?

• Comparison: Microsoft #95 ($36.8 billion), Intel #102 ($34.2 billion)

• Fabrication award for 500 nm CMOS fabrication process

• AMI C5N process with academic design kit (NCSU CDK)

• 1.5 mm x 1.5 mm die size, multiple dies, packaging

EDA Tools

• Big companies, lots of money, 40 years of integrated circuit design experience, conferences, journals, powerful PCs… what’s the problem?

• IC CAD tools are difficult to use

• Written by electrical engineers (not professional programmers)
• Incredibly buggy
• Not documented
• Rely on ancient, outdated file formats for interoperability
• Still mostly rely on command-line interfaces
• Utilize outdated, primitive, buggy APIs for GUIs
• Inherently required to solve hard problems

• Place components, route wires

• Must utilize advanced heuristics that are only as good as fabrication process technology information and user input (garbage-in, garbage-out)

EDA Tools

• Cadence tools

• “IC-Tools” => IC5141 package (Linux)
• Collection of tools managed by Design Framework II (dfII)

• Virtuoso schematic/layout editor

• Analog Environment

• Spectre simulator

• Diva DRC, EXT, LVS

• Other Cadence tools

• SignalStorm => TSI42 package (Linux)
• Abstract Generator => DSMSE54 (Solaris)
• First Encounter => SOC42 package (Linux)

• Synopsys

• Design Compiler (Linux)

• Mentor

• HDL Designer (Linux)

What EDA Tools Can Do?

• Manual layout vs. EDA is like:

• Manual transmission vs. automatic transmission
• HTML programming vs. Frontpage
• Assembly code programming vs. compiled high-level language

• Manual layout for small, optimized designs will always be superior
• EDA techniques for larger-scale designs will always be superior (verification, reusability, NRE, etc.)
• Goal: do careful, manual design of smaller components (cells) and use EDA to combine them for large-scale design

What EDA Tools Can Do?

“My” Design Flow