Fundamentals of VLSI Chip Design

Fundamentals of VLSI Chip Design

INSTRUCTOR: TUMMALA BHANU

VLSI Design:

• What is VLSI?

• “Very Large Scale Integration”
• Defines integration level
• 1980s hold-over from outdatedtaxonomy for integration levels

• Obviously influenced from
frequency bands, i.e. HF, VHF, UHF

• Sources disagree on what is measured (gates or transistors?)

• SSI – Small-Scale Integration (0-102)
• MSI – Medium-Scale Integration (102-103)
• LSI – Large-Scale Integration (103-105)
• VLSI – Very Large-Scale Integration (105-107)
• ULSI – Ultra Large-Scale Integration (>=107)

Integration Level Trends:

Obligatory historical Moore’s law plot

Integrated Circuits/MEMs:

• Today, VLSI refers to systems impl. w/integrated circuits

• Integrated circuit refers mostly togeneral manufacturing technique

• micro/nano-scale devices on a semiconductor (crystalline) substrate

• Formed using chemical/lithography processing

• What kind of devices / structures?

• transistors (bipolar, MOSFET)
• wires (interconnects and passive devices)
• diodes (junction, LEDs, VCSELs, MSM, photoconductor, PiN)

• MEMs (integration of piezoelectrics and mechanics based on static electrical fields: accelerometers, gyroscopes, pressure sensors, micro-mirrors)

• For CMOS digital design, we only use MOSFET transistors (used as switches) and wires

Chips:

• Integrated circuits consist of:
• A small square or rectangular “die”, < 1mm thick

• Small die: 1.5 mm x 1.5 mm => 2.25 mm2

• Large die: 15 mm x 15 mm =>

225 mm2

• Larger die sizes mean:

• More logic, memory

• Less volume

• Less yield

• Dies are made from silicon (substrate)

• Substrate provides mechanical support and electrical common point

VLSI Design:

• Draw polygons that represent layers deposited-on or infused-into the substrate

• More of an art than science

• One 2-input NAND gate with 4 transistors

• Typical microprocessor contains 50 – 200 million transistors (10-50 million gates)

VLSI Design:

• Manual layout design is obviously not practical
• Design complexity:

• Manually drawing layout for a billion transistors would take too long

• Even if we could…

• How to verify (test) designs for functionality, speed, power, etc.?

• Complexity scales faster than actual design

• How to reuse designs?

• How to create human-readable designs?

• How to speed-up design process?

• These problems form a great deal of work

• Electronic Design Automation (EDA)
• a.k.a. CAD

• Advancing EDA technology, fabrication technology, designs and micro architectures, and IP form bulk of work (and money) in the industry

Course Overview:

• This course is called “Fundamentals of VLSI Chip Design”
• Focus on large-scale system design (CAD tools)
• CAD tools manage design and verification complexity
• What we have…

• Latest, most advanced CAD tools in the EDA industry

• Three primary players

• Synopsys, #258 ($1.2 billion revenue)

• Cadence Design Systems, #259 ($1.1 billion revenue)

• Mentor Graphics, ?

• Comparison: Microsoft #95 ($36.8 billion), Intel #102 ($34.2 billion)

• Fabrication award for 500 nm CMOS fabrication process

• AMI C5N process with academic design kit (NCSU CDK)

• 1.5 mm x 1.5 mm die size, multiple dies, packaging

EDA Tools

• Big companies, lots of money, 40 years of integrated circuit design experience, conferences, journals, powerful PCs… what’s the problem?

• IC CAD tools are difficult to use

• Written by electrical engineers (not professional programmers)
• Incredibly buggy
• Not documented
• Rely on ancient, outdated file formats for interoperability
• Still mostly rely on command-line interfaces
• Utilize outdated, primitive, buggy APIs for GUIs
• Inherently required to solve hard problems

• Place components, route wires

• Must utilize advanced heuristics that are only as good as fabrication process technology information and user input (garbage-in, garbage-out)

EDA Tools

• Cadence tools

• “IC-Tools” => IC5141 package (Linux)
• Collection of tools managed by Design Framework II (dfII)

• Virtuoso schematic/layout editor

• Analog Environment

• Spectre simulator

• Diva DRC, EXT, LVS

• Other Cadence tools

• SignalStorm => TSI42 package (Linux)
• Abstract Generator => DSMSE54 (Solaris)
• First Encounter => SOC42 package (Linux)

• Synopsys

• Design Compiler (Linux)

• Mentor

• HDL Designer (Linux)

What EDA Tools Can Do?

• Manual layout vs. EDA is like:

• Manual transmission vs. automatic transmission
• HTML programming vs. Frontpage
• Assembly code programming vs. compiled high-level language

• Manual layout for small, optimized designs will always be superior
• EDA techniques for larger-scale designs will always be superior (verification, reusability, NRE, etc.)
• Goal: do careful, manual design of smaller components (cells) and use EDA to combine them for large-scale design

What EDA Tools Can Do?

“My” Design Flow

Steps involved in VLSI Design

VLSI Design

• There are many different “styles” of design

– Full custom

• Every gate is special

• Basically not done anymore

– Application Specific Integrated Circuits (ASIC)

• Gates all come from library, but connections all unique

– System on Chip (SOC)

• Chip consists of blocks that were all created before

• Silicon “printed circuit board”

• Real VLSI chips often use a little bit of all three styles in them

– Might be one custom analog block, ASIC gates, and a

couple of larger “IP” blocks

Levels of Abstraction

• Have different levels of details

– Top level is your goal

• Initially not executable

• Often becomes C++ code

– Then create microArch

• Rough hardware resources

• Rough communication

• Can be executable

– Functional Model

• Design is never top down or

bottom up. It is really iterations

to match the constraints on

both ends: hardware and spec.

Validation

• Remember that those polygons must match specification

– Ensure each implementation matches specification

• But typically only simulate the “system” at the top levels

– Automatic tools only work at the bottom levels

– Implies need to create a lot of testing infrastructure

• Use higher level simulation to drive and check implementation

• Check the correspondence using “formal methods” (math)

• VLSI design is mostly about validation

– Not about creating the circuit/function

– But about making sure that unit meets spec

• Functional, area, and power

Design Methodologies and Flows

• Design Flows:

– Left fork: Full custom

– Center fork: “ASIC”

– Right fork: System on Chip

Full Custom Design Flow

• Gives the designer the most freedom

– Lots of rope

• Can be clever

• Can hang yourselves too

• For a specific function

– Can achieve best performance

• Speed, power, area, etc

– Most work/time per function

– Optimizations are at a low level

• Circuit better be important

• Think assembler, only worse

Schematic Capture/Simulation

• Circuit drawn many levels

– Transistor, gate, and block

• Uses hierarchy

– Blocks inside other blocks

– Allows reuse of designs

• Tool create simulation netlists

– Components and all

connections

Layout

• Draw and place transistors for all

devices in schematic

• Rearrange transistors to

minimize interconnect length

• Connect all devices with routing

layers

• Possible to place blocks within

other blocks

– Layout hierarchy should

match schematic hierarchy

Design Rule Checking

• Fab has rules for the polygons

– Required for manufacturability

• DRC checker looks for errors

– Width

– Space

– Enclosure

– Overlap

– Lots of complex stuff (more later)

• Violations flagged for later fixup

Layout Versus Schematic

• Extracts netlist from layout

by analyzing polygon

overlaps

• Compares extracted netlist

with original schematic

netlist

• When discrepancies occur,

tries to narrow down

location

Layout Parasitic Extraction (LPE)

• Estimates capacitance between structures in the layout

• Calculates resistance of wires

• Output is either a simulation netlist or a file of interblock delays

“ASIC” Design Flow

• Separate teams to

design and verify

• Physical design is

(semi-) automated

• Loops to get device

operating frequency

correct can be

troubling

Register Transfer Level (RTL)

• Sections of combinational Goo separated by timing statements

– Defines behavior of part on every clock cycle boundary

Construct

Logic Synthesis

• Changes cloud of combinational

functionality into standard cells

(gates) from fab-specific library

• Chooses standard cell flipflop/

latches for timing

statements

• Attempts to minimize delay and

area of resulting logic

Standard Cell Placement and Routing

• Place layout for

each gate

(“cell”) in design

into block

• Rearrange cell

layouts to

minimize routing

• Connect up

cells

System On Chip Design Flow

• Can buy “Intellectual Property” (IP) from

various vendors

• “Soft IP”: RTL or gate level description

– Synthesize and Place and Route for

your process.

– Examples: Ethernet MAC, USB

• “Hard IP”: Polygon level description

– Just hook it up

– Examples: XAUI Backplane driver,

embedded DRAM

• Also: Standard cell libraries for ASIC flow

Chip Assembly

• Integrate blocks from previous steps

– Real chips have different types of

blocks

• Can resemble picture on right

– Key is to have a early plan

– And continue to update it

– Need to have accurate floorplan

• Early Floorplanning is key

– Sets the specs for the components

– Functional, physical, timing

Validation and Tape Out

• Making a mistake is very expensive

– Have a tool check all previous types of mistakes

• Check all errors, sign off on false positives, fix errors

– Run check tool again

• Tape out

– Used to write 9-track computer tapes for mask making

– Now, transfer polygons to fabrication company via ftp

• You’re done! (Except for documentation, test vector generation,

device bringup, skew lots, reliability tests, burnin…)

Evolution of Integrated Circuits

Background

– VLSI is pretty new; it has its beginning back in the early 60's with SSI, small scale integration, when a few bipolar transistors and resistors were fabricated on the same chip. Today chips are both simpler and more complex. They typically only contain two active elements (nMOS and pMOS transistors) and wires. But there might be billions of these transistors on the chip, and these chips can do amazing functions. You also find chips in everything. This lecture will look at why this has happened and what it hard about VLSI design.

Why Integrated Circuits?

• Break this question into two questions
– Why electronics
– Why use ICs to build electronics
• Why use electronics
– Electrons are easy to move / control
• Easier to move/control electrons than real stuff
– Move information, not things (phone, fax, WWW, etc.)
• Takes much less energy and $

From Tubes

1945 ENIAC filled an entire room!
17,468 vacuum tubes, 70,000 resistors, and 10,000 capacitors
6,000 manual switches and many blinking lights! could add 5,000 numbers in a single second.

To Transistors
1947
Point-contact transistor
1954
first computer with no tube, 800 transistors and 10,000 germanium crystal rectifiers. only 100 watts.

TX-0 (MIT) and the Transistor 1 (Manchester)













What is an Integrated Circuit?

• A device having multiple electrical components and their
interconnects manufactured on a single substrate.
• First IC 1958
– Jack Kilby at TI
– Germanium
– Wax support
– Made history










First Useful IC 1961

• Planar Process (Fairchild)
– Bob Noyce
– Silicon
• People initially named things
– SSI – Small scale
• 60’s
– MSI – Medium scale
• Early 70’s
– LSI – Large scale
• Late 70s
– VLSI – Very large scale
• Early 80’s











Electronics

• Building electronics:
– Started with tubes, then miniature tubes
– Transistors, then miniature transistors
– Components were getting cheaper, but:
• There is a minimum cost of a component (storage, handling …)
• Total system cost was proportional to complexity
• Integrated circuits changed that
– Printed a circuit, like you print a picture,
• Create components in parallel
• Cost no longer depended on # of devices
– What happens as resolution goes up?

Moore’s Law













• Original “law”: number of components on IC doubles every year
• Later modified to doubling every 18 months, later to 2 years, etc

Moore’s Law Today












• International Technology Roadmap for Semiconductors (ITRS)
– Projects roadmap for next 15 years
• Defined in terms of “Technology Nodes”
– Lithography of DRAM half pitch
• 2001 => 130nm (130nm)
• 2004 => 90nm
• 2013 => 32nm

Moore’s Law

First stated by Intel’s Gordon Moore in the mid 60’s. Saw that the resolution of the printing process was improving exponentially (0.7x feature size every 3 years) and predicted that it would continue into the future Since the cost of the printing process (called wafer fabrication) was growing at a modest rate, it implied that the cost per function, was dropping exponentially. At each new generations, each gate cost about 1/2 what it did 3 years ago. Shrinking an existing chip makes it cheaper!

Average Transistor Cost











How Much Can We Put on a Chip?











• An incredible number of gates
• Caveat: these are upper bounds
– Dies this big don’t yield well (if at all)
– 300l2 gate is minimum size
– DRAM cell efficiency is only about 50%
• One 12 inch DRAM wafer in 2013 will contain about 4 trillion bits (!)

Perspective: In Your Lifetime

• Most of you were born 1983 +- a few years
• Cray-1: world’s fastest computer 1976-1982
– 64Mb memory (50ns cycle time)
– 40Kb register (6ns cycle time)
– ~1 million gates (4/5 input NAND)
– 80MHz clock
– 115kW
• In 90nm technology
– 64Mb => 9mm2
– 1 million NAND-4 gates => 4mm2
– 40Kb register => 0.13mm2
– Fits in a 3.5mm x 3.5mm die











Good News, but…

• Some things getting worse with each generation:
– Complexity
• How do you know it will do what you really want in the end
– Power
• Need to worry about how to dissipate the heat
• Supply the energy (and route it to the needed place)
– Noise – Signal integrity, smaller margins, coupling
– Robustness / Reliability
• Soft errors, hard errors, defects, variations
– Non recurring engineering costs (NRE)
• Design time, CAD tools
• Mask costs (tooling needed to create IC)
• NRE fabrication charges (fabs are VERY expensive)

The Bad News

• Although the cost of manufacturing IC's
remained approximately constant, the
design cost did not. In fact, while designer
productivity has improved with time, it has
not increased a the same rate as the
complexity of the chips.
• So the cost of the chip design is growing
exponentially with the complexity of the
circuit. The integrating of a system on a
piece of silicon has an attractive
manufacturing cost but frightening design
cost and risk. Need to build very complex
stuff.
• Many chip costs are dominated by
amortized design cost and not fabrication
cost. ASIC design is $10-20M/chip, custom
design is larger than that











One Way Out: Use a Microprocessor
(Someone Else Paid For the VLSI Design)

• Pros:
– Intel and AMD have giant design teams – leverage them
– Cost of large support infrastructure spread over huge user community
– Tons of different micros
• From ARM to Intel, and don’t forget all the microcontrollers and DSPs
• Established software for most of them
• Cons:
– General purpose computer
• Not tuned to your application
• Not as efficient in execution
– Bad at bit twiddling
– But if it is good enough
• It will be a cheaper solution
• Unless you sell 1M units












Option 2: A Field Programmable Gate Array (FPGA)











• Configurable logic gates pre-fabricated with reconfigurable interconnect
– Now Xilinx and Altera have paid for the design cost
– And cost to build the support tools
• Pros:
– No NRE for the chip
– Very fast turnaround, easier to fix mistakes
– Configurations for often used functions readily available
– Can design at the gate level
• Cons:
– Practical number of usable gates is about 1 million at 0.13µ
• Reaching a clock frequency of 150MHz is doing well
• Power is typically 3x that of comparable Application Specific IC (ASIC)
– Chip cost for high-end parts is very high

Creating a Chip of Your Own

• Process is deceptively simple
– Similar to printing
• Choose a fabrication company (“fab”)
– Like choosing a printer
• Produce a set of negatives (“masks”)
– Like creating color layers
• 4 negatives for transistors
• 2 negatives per layer of wiring
• Send negatives and $$$ to fab
– Much more $$$ than printing
• Wait 2-3 months for fabrication
– Much slower than printing
• Package and test chips











The Hard Part – Managing Complexity

• Chips have zero tolerance for errors
• The previous example had eight polygons and two transistors
– A real design will have
• At least 1 million polygons and 100K transistors
• Any single error in any of the polygons can ruin the chip
• Easy to violate your power budget, speed target
• Mistakes are really expensive
– A full set of masks for 0.13µ is about $600,000
• No one person can really comprehend 1 million of anything
– much less 1 billion

VLSI Design – Complexity Management

• Simplify the design problem
– Create abstractions
• Simplified model for a thing,
• Works well in some subset of the design space
– Constraint designers – Create design methodology
• Needed to ensure that the abstractions are valid
• Might work if you violate constraints, but guarantees are off
– Enforce constraints
• Create tools to check the constraints
• Understand the underlying technology
– Provide a feeling for what abstractions and constraints are needed
– Determine efficient solutions (in design time, or implementation
area, power, or performance).

DEVELOPMENTS IN THE FIELD OF VLSI

There are a number of directions a person can take in VLSI, and they are all closely related to each other. Together, these developments are going to make possible the visions of embedded systems and ubiquitous computing.

1. Reconfigurable computing:
Reconfigurable computing is a very interesting and pretty recent development in microelectronics. It involves fabricating circuits that can be reprogrammed on the fly! And no, we are not talking about microcontrollers running with EEPROM inside. Reconfigurable computing involves specially fabricated devices called FPGA's, that when programmed act just like normal electronic circuits. They are so designed that by changing or "reprogramming" the connections between numerous sub modules, the FPGA's can be made to behave like any circuit we wish.

This fantastic ability to create modifiable circuits again opens up new possibilities in microelectronics. Consider for example, microprocessors which are partly reconfigurable. We know that running complex programs can benefit greatly if support was built into the hardware itself. We could have a microprocessor that could optimise itself for every task that it tackled! Or then consider a system that is too big to implement on hardware that may be limited by cost, or other constraints. If we use a reconfigurable platform, we could design the system so that parts of it are mapped onto the same hardware, at different times. One could think of many such applications, not the least of which is prototyping - using an FPGA to try out a new design before it is actually fabricated. This can drastically reduce development cycles, and also save some money that would have been spent in fabricating prototype IC's

2. Software Engineers taking over hardware design?:
ASIC's provide the path to creating miniature devices that can do a lot of diverse functions. But with the impending boom in this kind of technology, what we need is a large number of people who can design these IC's. This is where we realise that we cross the threshold between a chip designer and a systems designer at a higher level. Does a person designing a chip really need to know every minute detail of the IC manufacturing process? Can there be tools that allow a designer to simply create design specifications that get translated into hardware specifications?

The solution to this is rather simple - hardware compilers or silicon compilers as they are called. We know by now, that there exist languages like VHDL which can be used to specify the design of a chip. What if we had a compiler that converts a high level language into a VHDL specification? The potential of this technology is tremendous - in simple manner, we can convert all the software programmers into hardware designers!

3. The need for hardware compilers:
Before we go further let us look at why we need this kind of technology, that can convert high-level languages into hardware definitions. We see a set of needs which actually lead from one to the other in a series.

A. Rapid development cycles.
The traditional method of designing hardware is a long and winding process, going through many stages with special effort spent in design verification at every stage. This means that the time from drawing board to market, is very long. This proves to be rather undesirable in case of large expanding market, with many competitors trying to grab a share. We need alternatives to cut down on this time so that new ideas reach the market faster, where the first person to get in normally gains a large advantage.

B. Large number of designers.
With embedded systems becoming more and more popular, there is a need for a large number of chip designers, who can churn out chips designed for specific applications. Its impractical to think of training so many people in the intricacies of VLSI design.

C. Specialized training.
A person who wishes to design ASIC's will require extensive training in the field of VLSI design. But we cannot possibly expect to find a large number of people who would wish to undergo such training. Also, the process of training these people will itself entail large investments in time and money. This means there has to be system a which can abstract out all the details of VLSI, and which allows the user to think in simple system-level terms.

There are quite a few tools available for using high-level languages in circuit design. But this area has started showing fruits only recently. For example, there is a language called Handel-C, that looks just like good old C. But it has some special extensions that make it usable for defining circuits. A program written in Handel-C, can be represented block-by-block by hardware equivalents. And in doing all this, the compiler takes care of all low-level issues like clock-frequency, layout, etc. The biggest selling point is that the user does not really have to learn anything new, except for the few extensions made to C, so that it may be conveniently used for circuit design.

Another quite different language, that is still under development, is Lava. This is based on an esoteric branch of computer science, called "functional programming". FP itself is pretty old, and is radically different from the normal way we write programs. This is because it assumes parallel execution as a part of its structure - its not based on the normal idea of "sequence of instructions". This parallel nature is something very suitable for hardware since the logic circuits are is inherently parallel in nature. Preliminary studies have shown that Lava can actually create better circuits than VHDL itself, since it affords a high-level view of the system, without losing sight of low-level features.

MOST OF TODAY’S VLSI DESIGNS ARE CLASSIFIED INTO THREE CATEGORIES

1. Analog:
Small transistor count precision circuits such as Amplifiers, Data converters, filters, Phase Locked Loops, Sensors etc.

2. ASICS or Application Specific Integrated Circuits:
Progress in the fabrication of IC's has enabled us to create fast and powerful circuits in smaller and smaller devices. This also means that we can pack a lot more of functionality into the same area. The biggest application of this ability is found in the design of ASIC's. These are IC's that are created for specific purposes - each device is created to do a particular job, and do it well. The most common application area for this is DSP - signal filters, image compression, etc. To go to extremes, consider the fact that the digital wristwatch normally consists of a single IC doing all the time-keeping jobs as well as extra features like games, calendar, etc.

3. SoC or Systems on a chip:
These are highly complex mixed signal circuits (digital and analog all on the same chip). A network processor chip or a wireless radio chip is an example of an SoC.

THE VLSI DESIGN PROCESS

A Typical digital design flow is as follows:

• Specification
• Architecture
• RTL Coding
• RTL Verification
• Synthesis
• Backend
• Tape Out to Foundry (to get end product….a wafer with repeated number of identical Ics).
  

All modern digital designs start with a designer writing a hardware description of the IC (using HDL or Hardware Description Language) in Verilog/VHDL. A Verilog or VHDL program essentially describes the hardware (logic gates, Flip-Flops, counters etc) and the interconnect of the circuit blocks and the functionality. Various CAD tools are available to synthesize a circuit based on the HDL. The most widely used synthesis tools come from two CAD companies. Synposys and Cadence.

Without going into details, we can say that the VHDL, can be called as the "C" of the VLSI industry. VHDL stands for "VHSIC Hardware Definition Language", where VHSIC stands for "Very High Speed Integrated Circuit". This languages is used to design the circuits at a high-level, in two ways. It can either be a behavioural description, which describes what the circuit is supposed to do, or a structural description, which describes what the circuit is made of. There are other languages for describing circuits, such as Verilog, which work in a similar fashion.

Both forms of description are then used to generate a very low-level description that actually spells out how all this is to be fabricated on the silicon chips. This will result in the manufacture of the intended IC.


A Typical analog design flow is as follows:

In case of analog design, the flow changes somewhat.

• Specifications
• Architecture
• Circuit Design
• SPICE Simulation
• Layout
• Parametric Extraction / Back Annotation
• Final Design
• Tape Out to foundry.

While digital design is highly automated now, very small portion of analog design can be automated. There is a hardware description language called AHDL but is not widely used as it does not accurately give us the behavioral model of the circuit because of the complexity of the effects of parasitic on the analog behavior of the circuit. Many analog chips are what are termed as “flat” or non-hierarchical designs. This is true for small transistor count chips such as an operational amplifier, or a filter or a power management chip. For more complex analog chips such as data converters, the design is done at a transistor level, building up to a cell level, then a block level and then integrated at a chip level. Not many CAD tools are available for analog design even today and thus analog design remains a difficult art. SPICE remains the most useful simulation tool for analog as well as digital design.